140CPU31110 交流同服的技术本身就是借鉴并应用了变频的技术

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140CPU31110 交流同服的技术本身就是借鉴并应用了变频的技术

140CPU31110模块
交流同服的技术本身就是借鉴并应用了变频的技术，在直流电机的伺服控制的基础上通过变频的PWM方式模仿直流电机的控制方式来实现的，也就是说交流同服电机必然有变频的这一环节:变频就是将工频的50、60HZ的交流电先整流成直流电，然后通过可控制门极的各类晶体管(IGBT，IGCT等)通过载波频率和PWM调节逆变为频率可调的波形类以于正余弦的脉动电，由于频率可调，所以交流电机的速度就可调了 (n=60f/p，n转速，倾率，p极对数)

140CPU31110模块

CPU的分类还可以按照指令集的方式将其分为精简指令集计算机(RISC)和复杂指令集计算机(CISC)。RISC指令长度和执行时间恒定，CISC指令长度和执行时间不一定。 RISC 指令的并行的执行程度更好，并且编译器的效率也较高。CISC指令则对不同的任务有着更好的优化，代价是电路复杂且较难提高并行度，典型的CISC指令集有x86微架构，典型的RISC指令集有ARM微架构。但在现代处理器架构中RISC和CISC指令均会在译码环节进行转换，拆分成CPU内部的米RISC指今

140CPU31110 交流同服的技术本身就是借鉴并应用了变频的技术

40CPU31110 Module
The technology of AC co-service itself is to learn from and apply the technology of frequency conversion, which is realized by imitating the control mode of DC motor through the PWM mode of frequency conversion on the basis of the servo control of DC motor, that is to say, AC co-service motor must have the link of frequency conversion: frequency conversion is the power frequency of 50, 60HZ AC power first rectified into direct current. Then through the control gate of all kinds of transistors (IGBT, IGCT, etc.) through the carrier frequency and PWM to adjust the inverter frequency adjustable waveform class to the sine and cosine pulse electricity, because the frequency is adjustable, so the speed of the AC motor is adjustable (n=60f/p, n speed, tilt rate, p pole number)

140CPU31110 Module

The classification of cpus can also be divided into reduced instruction set computers (RISC) and complex instruction set computers (CISC) in terms of instruction sets. RISC instruction length and execution time are constant, CISC instruction length and execution time are not necessarily. The parallel execution of RISC instructions is better, and the compiler is more efficient. CISC instructions are better optimized for different tasks, but the cost is that the circuit is complex and difficult to improve the parallelism. Typical CISC instruction set has x86 microarchitecture, and typical RISC instruction set has ARM microarchitecture. However, in modern processor architectures, RISC and CISC instructions are converted in the decoding process, and are split into the internal RISC of the CPU