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5SHY4045L0003 址周期内发生多次总线传输 使数据总线保持三态
5SHY4045L0003一个地址周期内发生多次总线传输
使数据总线保持三态，并驱动read引脚。当数据就绪时，从卡将读取数据驱动到数据总线上，并将数据选通引脚驱动到低电平。信令方案是异步的，这意味着传输不依赖于总线时钟引脚的时序(与同步总线不同，如计算机与其外围设备互联标准).
块传输协议允许在一个地址周期内发生多次总线传输。在块传输模式下，第一次传输包括一个地址周期，随后的传输只需要数据周期。从机负责确保这些传输使用连续的地址。
总线主控可以通过两种方式释放总线。完成后释放(RWD)，主机在完成一次传输后释放总线，并且在每次后续传输前必须对总线进行重新仲裁。对于请求释放(ROR ),主机通过在两次传输之间继续置位BBSY来保留总线。ROR允许主设备保持对总线的控制，直到另一个希望对总线进行仲裁的主设备断言总线清除(BCLR)。因此，产生突发流量的主机可以优化它的通过仅在每个突发的第一次传输时仲裁总线来提高性能。这种传输延迟的降低是以其他主机的传输延迟稍高为代价的。
地址修饰符用于将VME总线地址空间分成几个不同的子空间。地址修饰符是底板上的一组6位宽的信号。地址修饰符指定有效地址位数、特权模式(允许处理器区分用户级或系统级软件的总线访问)，以及传输是否为块传输。
5SHY4045L0003 址周期内发生多次总线传输 使数据总线保持三态
SHY4045L0003 Multiple bus transfers occur within an address cycle
Keeps the data bus in three states and drives the read pin. When the data is ready, the slave card will read the data drive onto the data bus and drive the data strobe pin to a low level. The signaling scheme is asynchronous, meaning that the transmission does not depend on the timing of the bus clock pin (unlike a synchronous bus, such as the computer interconnection standard with its peripherals).
The Block Transport protocol allows multiple bus transfers to occur within an address cycle. In block transfer mode, the first transfer includes one address cycle, and subsequent transfers only require data cycles. The slave is responsible for ensuring that these transmissions use continuous addresses.
The bus master can release the bus in two ways. Release after Completion (RWD), the host releases the bus after completing a transfer and must re-arbitrate the bus before each subsequent transfer. For request release (ROR), the host preserves the bus by continuing to set BBSY between transfers. ROR allows the master device to maintain control of the bus until another master device that wishes to arbitrate the bus asserts bus Cleanup (BCLR). Therefore, a host generating burst traffic can optimize its performance by arbitrating the bus only on the first transmission of each burst. This reduction in transmission latency comes at the expense of slightly higher transmission latency on other hosts.
Address modifiers are used to divide the VME bus address space into several different subspaces. An address modifier is a set of 6-bit-wide signals on the backplane. Address modifiers specify valid address bits, privileged mode (which allows the processor to distinguish bus access for user-level or system-level software), and whether the transfer is a block transfer.
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